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Lecturer(s)
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Beltran Prieto Luis Antonio, MSc.
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Vlček Karel, prof. Ing. CSc.
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Pospíšilík Martin, Ing. Ph.D.
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Kunčar Aleš, Ing.
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Janků Peter, Ing. Ph.D.
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Course content
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Basic words and syntax of VHDL. - Model design. - Model simulation. - The "Test-Bench" creation. - The definition of initial conditions of simulation. - The periodic signal modeling. - Design of hierarchical models. - The rules of abstraction level of parts of hierarchical models. - Sensitivity list. - Event control of simulation. - The "Intellectual Property Cores" application. - "Package" application. - Time modeling. - Logic synthesis.
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Learning activities and teaching methods
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Lecturing, Simple experiments, Exercises on PC
- Participation in classes
- 56 hours per semester
- Home preparation for classes
- 10 hours per semester
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| learning outcomes |
|---|
| Knowledge |
|---|
| Student is able to design digital circuits and systems. Student can interpret simulated timing diagrams. Student will aquire the ability to insert IP blocks into the design. |
| Student is able to design digital circuits and systems. Student can interpret simulated timing diagrams. Student will aquire the ability to insert IP blocks into the design. |
| teaching methods |
|---|
| Lecturing |
| Simple experiments |
| Simple experiments |
| Lecturing |
| Exercises on PC |
| Exercises on PC |
| assessment methods |
|---|
| Written examination |
| Written examination |
| Oral examination |
| Oral examination |
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Recommended literature
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COHEN, B. VHDL Cosiny Styles, and Methodologies. Kluwer Academic Publishers, 1999.
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Musil, Vlček. Návrh číslicových obvodů. Brno.
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Vlček, K. a kol. Návrh digitálních integrovaných obvodů - Jazyk VHDL. VUT Brno, 2000. ISBN 80-214-1750-1.
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Vlček, Karel. Komprese a kódová zabezpečení v multimediálních komunikacích. 2. vyd. Praha : BEN - technická literatura, 2004. ISBN 80-7300-134-9.
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